1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices, and more particularly to a gate conductor isolation process of a vertical DRAM cell.
2. Discussion of Related Art
The manufacture and design of integrated circuits has greatly increased in sophistication, including the isolation of gate conductors. Increased integration density leads to economic advantages as increased numbers of devices and circuits may be placed on a single chip and/or within a single package (which may include a plurality of chips). Performance improvements such as achieved as integration density is increased may be due to a reduction in length of signal paths, capacitance between connections and the like. The performance gain is important in integrated circuits.
Integrated circuits such as dynamic access memories (DRAMs) can have millions of similar devices on a single chip, collectively referred to as an array or array portion of the chip design. The devices are controlled throughout the chip or partitions thereof by circuits such as addressing circuits, sense amplifiers and the like, referred to as support circuits.
Circuit requirements may be different for the array and support regions of the chip, and may need different processes during manufacture. For example, the current integration process for vertical array DRAM results in an insufficient process window for the formation of an array top oxide needed for the isolation of passing wordline to an active area.
In view of the foregoing and other problems of chip architecture, a need exists for a method for a gate conductor isolation process for a semiconductor memory device, the memory device including an array area and a support area.